The present invention describes a new technique of successive approximation.
The successive approximation algorithm is well known. One application for the success of approximation algorithm is in a column parallel A to D converter of the type described in U.S. Pat. No. 5,471,515. Each value from each column needs to be A to D converted. A successive approximation converter has been found to represent a good tradeoff between quality, speed, and size on the die.
One problem with the successive approximation system, however, is settling time of the capacitors that are used. This limits the speed of such a device.
The present disclosure describes a new successive approximation technique called the Error-Correcting Successive Approximation Technique. This technique uses multiple comparisons per clock cycle, e.g. two comparisons per clock cycle. While double the number of comparisons are needed, the way in which the comparisons are carried out obviates the need for accurate settling and comparison at each clock cycle. two comparisons are used at each clock cycle, each of which requires less resolution. While twice as many cycles are needed, the overall conversion time can still be significantly reduced.